Architecture design of a high-performance mass memory unit based on Xilinx Versal FPGA for future space applications

Abstract

Modern satellites carry increasingly complex and potent payload systems that produce valuable data for scientific or commercial purposes. These payloads generate high amounts of data in short timeframes which commonly exceeds the capacity of the available downlink channels. This, coupled with sparse contact windows to the ground station, necessitates a way to store payload data on-board for later transmission to ground. Therefore, mass memory units are key components of modern observation satellites. They provide the capability to store and retrieve payload data as well as housekeeping data generated on the satellite. In this paper the current status of a high-performance but reliable MMU development for next generation satellite systems based on a Microchip RTG4 and a Xilinx Versal FPGA is presented. The proposed design will reach data rates up to 20 Gbit s-1 with a storage capacity of more than 48 Tbit. To this end the architectural design implementation details are shown.