FPGA-based digital twin approach for design and test

Abstract

A Digital Twin (DT) simulates a product for a special purpose in sufficient detail for that purpose. Our purpose in this article is to utilize DTs in the test program set (TPS) development for automatic test equipment (ATE). Such a DT will provide for a much-needed mechanism to develop and verify test programs. Throughout this article electronic circuits represent the products and testing the product is the special purpose. A DT mimicking a unit under test (UUT) is a well-established methodology for supporting test and test development. Usually DTs are software-implemented and therefore, their use is limited to low-complexity electronic circuits. With lots of integrated circuits on today's circuit boards simulating them is challenging. Emulation instead of simulation can overcome the software limitations to a certain degree. Field Programmable Gate Arrays (FPGAs) then serve as the implementation platform for emulating hardware by means of configurable hardware. Due to their special properties, FPGAs are best suited for emulating data flow-oriented functional parts of the emulated circuits. However, when it comes to memory-intensive applications with branched processes, FPGAs cannot exploit their advantages particularly well. If the emulated system has a balanced need for data flow-oriented and irregular emulation elements, combination with a processor system would be an option. Today, FPGA vendors offer powerful devices for building a system on a programmable chip (SoPC). SoPCs have a multi-core processing system (PS) supplemented with a programmable logic (PL) on a single chip which allows for high bandwidth and low latency connectivity between PS and PL. The PS has a broad range of standard interfaces typical for microcontrollers including Ethernet. Based on all these properties of an FPGA-based solution, we propose a DT methodology that allows the DT to be developed during the DUT development to such an extent that the test development can be started concurrently.