FPGA-based accelerator method for Edge Computing

Abstract

Edge computing helps radio-supported mobile systems to process computing tasks on the side ofservers. The proximity to an edge computing node avoids excessive latencies, which benefits the calculation ofreal-time algorithms. Special computing needs arise because mobile systems are often so limited in weight andenergy that they cannot carry powerful on-board computers. We propose the use of FPGA-based co-processors(FPGA: Field Programmable Gate Array) to handle computations in an edge node. The calculation of the FastFourier Transformation (FFT) will be presented as an example of a co-processor. The use of FPGA-based co-processors poses a particular challenge when a mobile system leaves its radio cell, and the computing contextmust be transferred to another edge node. The article first addresses specific edge computing requirements,such as case-by-case reconfiguration of computing hardware and the handover mechanism from one edge nodeto another. Using the example of an FPGA-based FFT co-processor, we describe its development, which wascarried out under the condition that mobile clients can request different co-processors and that they can alsochange the edge node when changing the radio cell. The latter requires passing the co-processor context. Forthe FPGA, this means that the co-processor is part of a partially reconfigurable environment and must supportthe handover mechanisms in hardware. At the end we indicate the need for FPGA resources and compare thiswith alternative solutions.