VHDL Design und Implementierung eines CAN-Controllers in einem FPGA

Hillebrecht, Simon

DC Element	Wert	Sprache
dc.contributor.advisor	Schäfers, Michael	-
dc.contributor.author	Hillebrecht, Simon
dc.date.accessioned	2020-09-29T10:43:01Z	-
dc.date.available	2020-09-29T10:43:01Z	-
dc.date.created	2010
dc.date.issued	2010-09-28
dc.identifier.uri	http://hdl.handle.net/20.500.12738/5168	-
dc.description.abstract	In dieser Bachelorarbeit wird ein CAN-Controller in VHDL designed und in einem FPGA implementiert.	de
dc.description.abstract	This bachelor thesis descripes the design of an CAN-controller in VHDL and its implementation in an FPGA.	en
dc.language.iso	de	de
dc.rights.uri	http://rightsstatements.org/vocab/InC/1.0/	-
dc.subject.ddc	004 Informatik
dc.title	VHDL Design und Implementierung eines CAN-Controllers in einem FPGA	de
dc.type	Thesis
openaire.rights	info:eu-repo/semantics/openAccess
thesis.grantor.department	Department Informatik
thesis.grantor.place	Hamburg
thesis.grantor.universityOrInstitution	Hochschule für angewandte Wissenschaften Hamburg
tuhh.contributor.referee	Heitmann, Hans Heinrich	-
tuhh.gvk.ppn	635704110
tuhh.identifier.urn	urn:nbn:de:gbv:18302-reposit-51708	-
tuhh.note.extern	publ-mit-pod
tuhh.note.intern	1
tuhh.oai.show	true	en_US
tuhh.opus.id	1063
tuhh.publication.institute	Department Informatik
tuhh.type.opus	Bachelor Thesis	-
dc.subject.gnd	VHDL
dc.subject.gnd	Field programmable gate array
dc.type.casrai	Supervised Student Publication	-
dc.type.dini	bachelorThesis	-
dc.type.driver	bachelorThesis	-
dc.type.status	info:eu-repo/semantics/publishedVersion
dc.type.thesis	bachelorThesis
dcterms.DCMIType	Text	-
tuhh.dnb.status	domain	-
item.advisorGND	Schäfers, Michael	-
item.languageiso639-1	de	-
item.fulltext	With Fulltext	-
item.creatorGND	Hillebrecht, Simon	-
item.openairetype	Thesis	-
item.grantfulltext	open	-
item.creatorOrcid	Hillebrecht, Simon	-
item.cerifentitytype	Publications	-
item.openairecristype	http://purl.org/coar/resource_type/c_46ec	-
Enthalten in den Sammlungen:	Theses